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Features
Single Power Supply Read and Write Voltage, 5 V 5% High Performance 200 ns Maximum Access Time 6 ms Typical Sector Write CMOS Low Power Consumption 20 mA Typical Active Current (Byte Mode) 400 A Typical Standby Current Fully MS-DOS Compatible Flash Driver and Formatter Virtual-Disk Flash Driver with 512 Bytes/Sector Random Read/Write to any Sector No Erase Operation Required Prior to any Write Zero Data Retention Power Batteries not Required for Data Storage PCMCIA/JEIDA 68-Pin Standard Selectable Byte- or Word-Wide Configuration High Re-programmable Endurance Built-in Redundancy for Sector Replacement Minimum 100,000 Write Cycles Five Levels of Write Protection Prevent Accidental Data Loss
2-Megabyte Flash Memory PCMCIA Card AT5FC002
Block Diagram
Pin Configuration
Pin Name A0-A20 D0-D15 CE1, CE2, WE, OE, REG CD, WP BVD1, BVD2 Function Addresses Data Control Signals Card Status
Description
Atmel's Flash Memory Card provides the highest system level performance for data and file storage solutions to the portable PC market segment. Data files and applications programs can be stored on the AT5FC002. This allows OEM manufacturers of portable system to eliminate the weight, power consumption and reliability issues associated with electro-mechanical disk-based systems. The AT5FC002 requires a single voltage power supply for total system operation. No batteries are needed for data retention due to its Flash-based technology. Since no high voltage (12-volt) is required to perform any write operation, the AT5FC002 is suitable for the emerging "mobile" personal systems. The AT5FC002 is compatible with the 68-pin PCMCIA/JEIDA international standard. Atmel's Flash Memory Cards can be read in either a byte-wide or word-wide mode which allows for flexible integration into various system platforms. It can be read like any typical PCMCIA SRAM or ROM card. The Card Information Structure (CIS) can be written by the OEM or by Atmel at the attribute memory address space using a format utility. The CIS appears at the beginning of the card's attribute memory space and defines the low-level organization of data on the PC card. The AT5FC002 contains a separate 2 Kbyte EEPROM memory for the card's attribute memory space. The third party software solutions such as AWARD Software's CardWareTM system and the SCM's Flash File System (FFS), enables Atmel's Flash Memory Card to emulate the function of essentially all the major brand personal computers that are DOS/Windows compatible. For some unique portable computers, such as the HP200/100/95LX series, the software Driver and Formatter are also available. The Atmel Driver and Formatter utilizes a selfcontained spare sector replacement algorithm, enabled by Atmel's small 512-byte sectors, to achieve long term card reliability and endurance.
Block Diagram
2
AT5FC002
AT5FC002
Absolute Maximum Ratings*
Storage Temperature........................ -30C to +70C Ambient Temperature with Power Applied................................... -10C to +70C Voltage with Respect to Ground, All pins(1).......... -2.0 V to +7.0 V VCC(1) ............................................... -2.0 V to +7.0 V Output Short Circuit Current (2) .................... -200 mA
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the card. This is a stress rating only and functional operation of the card at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transients, inputs may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC+0.5 V. During voltage transitions, outputs may overshoot to VCC+2.0 V for periods up to 20 ns. 2. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. Conditions equal VOUT = 0.5 V or 5.0 V, VCC = Max.
D.C. and A.C. Operating Range
AT5FC002-20 Operating Temperature (Case) VCC Power Supply Com. 0oC - 70oC 5 V 5%
Pin Capacitance (f = 1 MHz, T = 25C) (1)
Symbol CIN1 COUT CIN2 CI/O
Note:
Parameter Address Capacitance Output Capacitance Control Capacitance I/O Capacitance
Conditions VIN = 0 V VOUT = 0 V VIN = 0 (CE) VI/O = 0 V
Typ
Max 20 20 45 20
Units pF pF pF pF
1. This parameter is characterized and is not 100% tested.
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PC Card Pin Assignments
I = Input, O = Output, I/O = Bi-directional, NC = No Connect Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE NC VCC NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND I I I I I I I I I I I I/O I/O I/O O I/O I/O I/O I/O I/O I I I I I I I I I I/O Function Ground Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Card Enable 1 Address Bit 10 Output Enable Address Bit 11 Address Bit 9 Address Bit 8 Address Bit 13 Address Bit 14 Write Enable No Connect Power Supply No Connect Address Bit 16 Address Bit 15 Address Bit 12 Address Bit 7 Address Bit 6 Address Bit 5 Address Bit 4 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 Data Bit 0 Data Bit 1 Data Bit 2 Write Protect Ground
(1) (1)
Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Signal GND CD1 D11 D12 D13 D14 D15 CE2 NC RFU RFU A17 A18 A19 A20 NC VCC NC NC NC NC NC NC NC NC NC REG BVD2 BVD1 D8 D9 D10 CD2 GND
I/O O I/O I/O I/O I/O I/O I
Function Ground Card Detect 1 (1) Data Bit 11 Data Bit 12 Data Bit 13 Data Bit 14 Data Bit 15 Card Enable 2 (1) No Connect Reserved Reserved
I I I I
Address Bit 17 Address Bit 18 Address Bit 19 Address Bit 20 No Connect Power Supply No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect
I O O I/O I/O I/O O
Register Select Battery Voltage Detect 2 (2) Battery Voltage Detect 1 (2) Data Bit 8 Data Bit 9 Data Bit 10 Card Detect 2 (1) Ground
Notes: 1. Signal must not be connected between cards. 2. BVD = Internally pulled up.
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AT5FC002
AT5FC002
Pin Description
Symbol A0-A20 Name Address Inputs Type Input Input/Output Function Address Inputs are internally latched during write cycles. Data Input/Outputs are internally latched on write cycles. Data outputs are latched during read cycles. Data pins are active high. When the memory card is de-selected or the outputs are disabled the outputs float to tri-state. Card Enable is active low. The memory card is de-selected and power consumption is reduced to standby levels when CE is high. CE activates the internal memory card circuitry that controls the high and low byte control logic of the card, input buffers, segment decoders, and associated memory devices. Output Enable is active low and enables the data buffers through the card outputs during read cycles. Write Enable is active low and controls the write function to the memory array. The target address is latched on the falling edge of the WE pulse and the appropriate data is latched on the rising edge of the pulse. PC Card Power Supply for device operation (5.0 V 5%) Ground Output Output When Card Detect 1 and 2 = Ground the system detects the card. Write Protect is active high and indicates that all card write operations are disabled by the write protect switch. Corresponding pin is not connected internally. Output Input Internally pulled up. (There is no battery in the card.) Provide access to Card Information Structure in the Attribute Memory Device
D0-D15
Data Input/Output
CE1, CE2
Card Enable
Input
OE
Output Enable
Input
WE
Write Enable
Input
VCC GND CD1, CD2 WP NC BVD1, BVD2 REG
PC Card Power Supply Ground Card Detect Write Protect No Connect Battery Voltage Detect Register Select
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Memory Card Operations
The AT5FC002 Flash Memory Card is organized as an array of 4 individual AT29C040A devices. They are logically defined as contiguous sectors of 512 bytes. Each sector can be read and written randomly as designated by the host. There is NO need to erase any sector prior to any write operation. Also, there is NO high voltage (12 V) required to perform any write operations. The common memory space data contents are altered in a similar manner as writing to individual Flash memory devices. Oncard address and data buffers activate the appropriate Flash device in the memory array. Each device internally latches address and data during write cycles. Refer to the Common Memory Operations table. first rising edge of CE or WE. Each byte pair to be programmed must have its high-to-low transition on WE (or CE) within 150 s of the low-to- high transition of WE (or CE) of the preceding byte pair. If a high-to-low transition is not detected within 150 s of the last low-to-high transition, the data load period will end and the internal programming period will start. All the bytes of a sector are simultaneously programmed during the internal programming period. A maximum write time of 10 ms per sector is self-controlled by the Flash devices. Refer to A.C. Write Waveforms drawings.
Write Protection
The AT5FC002 has five types of write protection. The PCMCIA/JEIDA socket itself provides the first type of write protection. Power supply and control pins have specific pin lengths in order to protect the card with proper power supply sequencing in the case of hot insertion and removal. A mechanical write protection switch provides a second type of write protection. When this switch is activated, WE is internally forced high. The Flash memory arrays are therefore write-disabled. The third type of write protection is achieved with the built-in low VCC sensing circuit within each Flash device. If the external VCC is below 3.8 V (typical), the write function is inhibited. The fourth type of write protection is a noise filter circuit within each Flash device. Any pulse of less than 15 ns (typical) on the WE, CE1 or CE2 inputs will not initiate a program cycle. The last type of write protection is based on the Software Data Protection (SDP) scheme of the AT29C040A devices. Each of the sixteen devices needs to enable and disable the SDP individually. Refer to the Software Data Protected Programming/Disable Algorithm tables for descriptions of enable and disable SDP operations.
Byte-Wide Operations
The AT5FC002 provides the flexibility to operate on data in byte-wide or word-wide operations. Byte-wide data is available on D0-D7 for read and write operations (CE1 = low, CE2 = high). Even and odd bytes are stored in a pair of memory chip segments (i.e., S0 and S1) and are accessed when A0 is low and high respectively.
Word-Wide Operations
The 16-bit words are accessed when both CE1 and CE2 are forced low, A0 = don't care. D0-D15 are used for word-wide operations
Read Enable/Output Disable
Data outputs from the card are disabled when OE is at a logichigh level. Under this condition, outputs are in the high-impedance state. The A20 selects the paired memory chip segments, while A0 decides the upper or lower bank. The CE1/CE2 pins determine either byte or word mode operation. The Output Enable (OE) is forced low to activate all outputs of the memory chip segments. The on-card I/O transceiver is set in the output mode. The AT5FC002 sends data to the host. Refer to A.C. Read Waveforms drawing.
Card Detection
Each CD (output) pin should be read by the host system to determine if the memory card is properly seated in the socket. CD1 and CD2 are internally tied to the ground. If both bits are not detected, the system should indicate that the card must be re-inserted.
Standby Operations
When both CE1 and CE2 are at logic-high level, the AT5FC002 is in Standby mode; i.e., all memory chip segments as well as the decoder/transceiver are completely de-selected at minimum power consumption. Even in the byte-mode read operation, only one memory chip segment (even or odd) is active at any time. The other seven memory chip segments remain in standby. In the word-mode there are two memory chip segments in active and six in standby.
CIS Data
The Card Information Structure (CIS) describes the capabilities and specifications of a card. The CIS of the AT5FC002 can be written either by the OEM or by Atmel at the attribute memory space beginning at address 00000H by using a format utility. The AT5FC002 contains a separate 2 Kbyte EEPROM memory for the card's attribute memory space. The attribute is active when the REG pin is driven low. D0-D7 are active during attribute memory access. D8-D15 should be ignored. Odd order bytes present invalid data. Refer to the Attribute Memory Operations table.
Write Operations
The AT5FC002 is written on a sector basis. Each sector of 512 bytes can be selected randomly and written independently without any prior erase cycle. A9 to A19 specify the sector address, while A20 specifies the Flash chip segment pair. Within each sector, the individual byte address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the
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AT5FC002
AT5FC002
Common Memory Operations
X = Don't Care, where Don't Care is either VIL or VIH levels. Pins Read-Only Read (x8) (1) Read (x8) Read (x8)
(2) (3)
REG
CE2
CE1
OE
WE
A0
D8-D15
D0-D7
VIH VIH VIH VIH VIH X
VIH VIH VIL VIL X VIH
VIL VIL VIH VIL X VIH
VIL VIL VIL VIL VIH X
VIH VIH VIH VIH VIH X
VIL VIH X X X X
High Z High Z Data Out-Odd Data Out-Odd High Z High Z
Data Out-Even Data Out-Odd High Z Data Out-Even High Z High Z
Read (x16) (4) Output Disable Standby Write-Only Write (x8) (1) Write (x8) (2) Write (x8)
(3)
VIH VIH VIH VIH VIH
VIH VIH VIL VIL X
VIL VIL VIH VIL X
VIH VIH VIH VIH VIH
VIL VIL VIL VIL VIL
VIL VIH X X X
High Z High Z Data In-Odd Data In-Odd High Z
Data In-Even Data In-Odd High Z Data In-Even High Z
Write (x16) (4) Output Disable
Notes: 1. Byte access - Even. In this x8 mode, D0-D7 contain the "even" byte (low byte) of the x16 word. D8-D15 are inactive. 2. Byte access - Odd. In this x8 mode, D0-D7 contain the "odd" byte (high byte) of the x16 word. This is accomplished internal to the card by transposing D8-D15 to D0-D7. D8-D15 are inactive.
3. Odd byte only access. In this x8 mode, D8-D15 contain the "odd" byte (high byte) of the x16 word. D0-D7 are inactive. A0 = X. 4. Word access. In this mode D0-D7 contain the "even" byte while D8-D15 contain the "odd" byte. A0 = X
Memory Card Program Routine
Byte Mode
Memory Card Program Routine
Word Mode
BEGIN
BEGIN
SELECT SECTOR LOAD ADDRESS/DATA OF 512 BYTES WAIT FOR A MAXIMUM OF 10 ms INTERLEAVING LOW 256 BYTES AND HIGH 256 BYTES
SELECT SECTOR LOAD ADDRESS/DATA OF 256 WORDS WAIT FOR A MAXIMUM OF 10 ms LOW AND HIGH BYTES SIMULTANEOUSLY
SECTOR PROGRAM COMPLETE
SECTOR PROGRAM COMPLETE
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Attribute Memory Operations
X = Don't Care, where Don't Care is either VIL or VIH levels. Pins Read-Only Read (x8) (1) Read (x8) Read (x8) Read (x16) Output Disable Standby Write-Only Write (x8) (1) Write (x8) Write (x8) Write (x16) Output Disable
Note:
REG
CE2
CE1
OE
WE
A0
D8-D15
D0-D7
VIL VIL VIL VIL VIL X
VIH VIH VIL VIL X VIH
VIL VIL VIH VIL X VIH
VIL VIL VIL VIL VIH X
VIH VIH VIH VIH VIH X
VIL VIH X X X X
High Z High Z Not Valid Not Valid High Z High Z
Data Out-Even Not Valid High Z Data Out-Even High Z High Z
VIL VIL VIL VIL VIL
VIH VIH VIL VIL X
VIL VIL VIH VIL X
VIH VIH VIH VIH VIH
VIL VIL VIL VIL VIL
VIL VIH X X X
High Z High Z Not Valid Not Valid High Z
Data In-Even Not Valid High Z Data In-Even High Z
1. Byte access - Even. In this x8 mode, D0-D7 contain the "even" byte (low byte) of the x16 word. D8-D15 are inactive.
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AT5FC002
AT5FC002
D.C. Characteristics, Byte-Wide Operation
Symbol ILI ILO ISB ICC1 (1) Parameter Input LeakageCurrent Output Leakage Current VCC Standby Current Condition VCC = VCC Max, VIN = VCC or VSS VCC = VCC Max, VOUT = VCC or VSS VCC = VCC Max, CE = VCC 0.2 V VCC = VCC Max, CE = VIL, OE = VIH, IOUT = 0 mA, at 5 MHz CE = VIL,WE = VIL, Programming in Progress Min Typ 1.0 1.0 0.4 Max 20 20 0.8 Units A A mA
VCC Active Read Current
20
40
mA
ICC2 VIL VIH VOL VOH
VCC Active Write Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
20
40 0.8
mA V V
2.4 IOL = 3.2 mA IOH = -2.0 mA 3.8 0.40
V V
Notes: 1. One Flash device active, 3 in standby.
D.C. Characteristics, Word-Wide Operation
Symbol ILI ILO ISB ICC1 (1) Parameter Input LeakageCurrent Output Leakage Current VCC Standby Current Condition VCC = VCC Max, VIN = VCC or VSS VCC = VCC Max, VOUT = VCC or VSS VCC = VCC Max, CE = VCC 0.2 V VCC = VCC Max, CE = VIL, OE = VIH, IOUT = 0 mA, at 5 MHz CE = VIL, WE = VIL, Programming in Progress Min Typ 1.0 1.0 0.4 Max 20 20 0.8 Units A A mA
VCC Active Read Current
40
80
mA
ICC2 VIL VIH VOL VOH
VCC Active Write Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
40
80 0.8
mA V V
2.4 IOL = 3.2 mA IOH = -2.0 mA 3.8 0.40
V V
Notes: 1. Two Flash devices active, 2 in standby.
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A.C. Read Characteristics
Symbol Parameter tRC tCE tACC tOE tLz tDF tOLZ tDF tOH tWC Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable to Output in Low Z Output Disable to Output in High Z Output Hold Time from First of Address, CE, or OE Change Write Recovery Time Before Read 5 10 5 60 5 60 Min 200 200 200 100 Max Units ns ns ns ns ns ns ns ns ns ms
Input test Waveforms and Measurement Level
3.0V AC DRIVING LEVELS 0.0V 1.5V AC MEASUREMENT LEVEL
Output Test Load
5.0V 1.8K OUTPUT PIN 1.3K 100pF
tR, tF < 5 ns
A.C. Read Waveforms (1)
POWER-UP, STANDBY ADDRESS DEVICE AND ADDRESS SELECTION OUTPUT DATA ENABLED VALID STANDBY, POWER-DOWN
ADDRESSES STABLE tRC
CE tDF OE tWC WE tCE tOLZ DATA 5.0 V 0V tLZ tACC VCC tOE tOH OUTPUT VALID HIGH Z tDF
Note: 1. CE refers to CE1, and/or CE2
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AT5FC002
AT5FC002
Write Cycle Characteristics
Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 100 10 60 60 10 100 150 Min Max 10 Units ms ns ns ns ns ns s ns
A.C. Write Waveforms (Byte Mode)
OE CE2 CE1 WE tAS A0 tAH tBLC tDH A1-A8 A9-A19 DATA
BYTE 0 BYTE 1 BYTE 2 BYTE 510 BYTE 511
BYTE ADDRESS SECTOR ADDRESS
tWP
tWPH tWC
tDS
Notes: 1. A20 specifies the pair of AT29C040A devices to be written, while A0 controls the selection of even and odd bytes. A0 and A20 must be valid throughout the entire WE low pulse. 2. A9 through A19 must specify the sector address during each high to low transition of WE (or CE).
3. OE must be high when WE and CE are both low. 4. All bytes that are not loaded within the sector being pro-
grammed will be indeterminate.
11
A.C. Write Waveforms (Word Mode)
OE CE1,2 WE tAS tAH A1-A8 A9-A19 DATA
WORD 0 WORD 1 WORD 2 WORD 254 WORD 255
BYTE ADDRESS SECTOR ADDRESS
tWP
tWPH tDH tBLC tWC
tDS
1. A20 specifies the pair of AT29C040A devices to be written; they must be valid throughout the entire WE low pulse. A0 is don't care. 2. A9 through A19 must specify the sector address during each high to low transition of WE (or CE).
3. OE must be high when WE and CE are both low. 4. All bytes that are not loaded within the sector being pro-
grammed will be indeterminate.
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AT5FC002
AT5FC002
Software Data Protected Programming Algorithm (1)
Device Data Address Data Address Data Address Writes Enabled
Note:
0 AA 00AAAA 55 005554 A0 00AAAA Write Bytes
1 AA 00AAAB 55 005555 A0 00AAAB Write Bytes
2 AA 10AAAA 55 105554 A0 10AAAA Write Bytes
3 AA 10AAAB 55 105555 A0 10AAAB Write Bytes
1. Load 3 bytes to corresponding Flash chip segment individually to enable software data protection.
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Software Data Protected Disable Algorithm (1)
Device Data Address Data Address Data Address Data Address Data Address Data Address Writes Enabled
Note:
0 AA 00AAAA 55 005554 80 00AAAA AA 00AAAA 55 005554 20 00AAAA Write Bytes
1 AA 00AAAB 55 005555 80 00AAAB AA 00AAAB 55 005555 20 00AAAB Write Bytes
2 AA 10AAAA 55 105554 80 10AAAA AA 10AAAA 55 105554 20 10AAAA Write Bytes
3 AA 10AAAB 55 105555 80 10AAAB AA 10AAAB 55 105555 20 10AAAB Write Bytes
1. Load 6 bytes to corresponding Flash chip segment individually to disable software data protection.
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AT5FC002
AT5FC002
Ordering Information
tACC (ns) 200 Ordering Code AT5FC002-20 Package PCMCIA Type 1 Operation Range Commercial (0C to 70C)
Packaging Information
PCMCIA, Type 1 PC Memory Card Dimensions in millimeters
85.6 0.2 mm
10.0 MIN. (mm)
54.0 0.1 mm
10.0 MIN. (mm)
3.3 0.1 mm 34 68 FRONT SIDE 1 35
BACK SIDE
CardWareTM may be trademarks of others.
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